Design and Implementation of Low Power High Speed Symmetric Decoder Structure for SDR Applications

  • Nidhin Sani
  • Agath Martin
  • Abin John Joseph
  • Nishanth R.
Keywords: Software Defined Radio(SDR), Tree Decoder, FPGA, HDL

Abstract

The key objective of this project is to design a decoder which can be used for hardware purposes. Hardware, here accompanies with software which is more we can discuss as a Software Defined Radio application. The decoder implemented here offers to new radio equipment (SDR), the flexibility of a programmable system. Nowadays, the behavior of a communication system can be modified by simply changing its software. Large tree decoder is made by reusing smaller similar sub-modules. Thus the structure is symmetric. The symmetric and regular structure of tree decoder makes the system a less complexity one. The structure obeys regularity and modularity concepts of VLSI circuit, thus is easy to fabricate using cell library elements. Design a Tree Decoder proposed architecture for SDR application on FPGA. The Structures made here are hardware synthesizable on FPGA board and are done in a respective manner. The design to be implementing by using Verilog-HDL language. The Simulation and Synthesis by using Xilinx Vivado design suite.

References

[1] A.F.B.Selva, A.L.G.Reis, K.G.Lenzi, L.G.P.Meloni, & S.E. Barbin. (2012). Introduction to the software-defined radio approach. IEEE Latin America Transactions, 10(1), 1156-1161.
[2] Anton S. Rodriguez, Michael C. Mensinger Jr., SooAhn, & Yufeng Lu. (2011). Model-based software- defined radio(SDR) design using FPGA. In IEEE International Conference on Electro/Information Technology (EIT), pp. 1-6.
[3] Timo, Vogt & Norbert When. (2008 Oct). A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment. In IEEE Transctions on VLSI, 16(10), 1309-1320.
[4] Arul D. Murugan, Hesham El Gamal, Mohamed Oussama Damen, & Giuseppe Caire. (2006). A unified framework for tree search decoding: rediscovering the sequential decoder. In IEEE Transactions on Information Theory, 52(3), 933-953.
[5] Seunghyun Beak, Van Hieu, B., Park, G., Kyungtaek Lee, & TaikyeongJeong. (1999). A new binary tree algorithm implementation with huffman decoder on FPGA. IEEE Transactions on communication, 47(10), 1455-1457.
[6] J. Mitola. (1993). Software radios: Survey, critical evaluation and future directions. In IEEE Aerospace and Electronics Systems Magazine, 8, pp. 25-36.
[7] RahulKumar & R.C.JoshiandRaju. (2009). A FPGA partial reconfiguration design approach for RASIPSDR. In IEEE Annual on India Conference, pp. 1-4.
[8] T. R. Padmanabhan & B. Bala Tripura Sundari. (2008). Design through verilog HDL. India: Wiley India Pvt Ltd.
[9] M. Morris Mano. (1984). Digital design. (2nd ed.). University of Michigan: Prentice-Hall.
[10] Charles H. Roth Jr. & Larry L. Kinney. (2004). Fundamentals of logic design. Available at: https://easyengineering.net/fundamentals-of-logic-design-by-roth/.
Published
2019-12-31
How to Cite
Nidhin Sani, Agath Martin, Abin John Joseph, & Nishanth R. (2019). Design and Implementation of Low Power High Speed Symmetric Decoder Structure for SDR Applications. International Journal of Engineering and Management Research, 9(6), 87-90. Retrieved from http://www.ijemr.net/ojs/index.php/ojs/article/view/22