Design and Implementation of Low Power High Speed Symmetric Decoder Structure for SDR Applications

Authors

  • Nidhin Sani Assistant Professor, Department of Information Technology, CUSAT/CUCEK, INDIA
  • Agath Martin Assistant Professor, Department of Information Technology, CUSAT/CUCEK, INDIA
  • Abin John Joseph Assistant Professor, Department of Electronics & Communication Engineering, CUSAT/CUCEK, INDIA
  • Nishanth R. Assistant Professor, Department of Electronics & Communication Engineering, CUSAT/CUCEK, INDIA

DOI:

https://doi.org/10.31033/ijemr.9.6.15

Keywords:

Software Defined Radio(SDR), Tree Decoder, FPGA, HDL

Abstract

The key objective of this project is to design a decoder which can be used for hardware purposes. Hardware, here accompanies with software which is more we can discuss as a Software Defined Radio application. The decoder implemented here offers to new radio equipment (SDR), the flexibility of a programmable system. Nowadays, the behavior of a communication system can be modified by simply changing its software. Large tree decoder is made by reusing smaller similar sub-modules. Thus the structure is symmetric. The symmetric and regular structure of tree decoder makes the system a less complexity one. The structure obeys regularity and modularity concepts of VLSI circuit, thus is easy to fabricate using cell library elements. Design a Tree Decoder proposed architecture for SDR application on FPGA. The Structures made here are hardware synthesizable on FPGA board and are done in a respective manner. The design to be implementing by using Verilog-HDL language. The Simulation and Synthesis by using Xilinx Vivado design suite.

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Published

2019-12-31

How to Cite

Nidhin Sani, Agath Martin, Abin John Joseph, & Nishanth R. (2019). Design and Implementation of Low Power High Speed Symmetric Decoder Structure for SDR Applications. International Journal of Engineering and Management Research, 9(6), 87–90. https://doi.org/10.31033/ijemr.9.6.15