Low Power and Simple Implementation of Secure Hashing Algorithm (SHA-2) using VHDL Implemented on FPGA of SHA-224/256 Core
Cryptography plays an important role in the security of data. Even though the data is encrypted it can be altered while transmitting on the network so data should be verified using a digital signature. Hashing algorithms are used to create these digital signatures for verification of the data received. Hashing algorithm like Secure Hash Algorithm-2 (SHA-2(224/256)) is designed which has a fixed output length of 512-bits.
Then to improve on power a low-power technique such as latch based clock gating technique is used. After applying these techniques all the designs are compared in terms of power, delay and frequency.
William Stallings. (2005). Cryptography and network security, Principles and Practices (IV). New Jersey: Prentice Hall.
NIST. (1995 August). Secure Hash Standard. Federal Information Processing Standards Publication, 180-1.
NIST. (2002 August). Secure Hash Standard. Federal Information Processing Standards Publication, 180-2.
NIST. (2008 August). Secure Hash Standard. Federal Information Processing Standards Publication, 180-3.
Harris E. Michail, & Athanasios S. Milidonis. (2009 October-December). A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores. IEEE Transaction on Dependable and Secure Computing, 6(4), 255-268.
N. Skluvos, G. Dimitroulakos & O. Koufopavlou. (2003 December). An Ultra High Speed Architecture for VLSI Implementation of Hash Functions. Electronics, Circuits and Systems, IEEE International Conference.
Copyright (c) 2018 International Journal of Engineering and Management Research
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.